#/*
# * Copyright {c} 2020-2021, SERI Development Team
# *
# * SPDX-License-Identifier: Apache-2.0
# *
# * Change Logs:
# * Date         Author          Notes
# * 2022-04-04   Lyons           first version
# */

# Note:
#   1. if work on Windows, you can use iverilog, Gowin FPGA or XEMU to simulate
#   2. if work on Linux, you can use VCS or XEMU to simulate

ifeq ($(shell uname), Linux)
EMBTOOLPATH     = /home/crazy/Tools/compiler/xuantie/v8.4.0/riscv64-elf-x86_64-20210307
EMBTOOLPREFIX   = ${EMBTOOLPATH}/bin/riscv64-unknown-elf
CC              = ${EMBTOOLPREFIX}-gcc
OBJDUMP         = ${EMBTOOLPREFIX}-objdump
OBJCOPY         = ${EMBTOOLPREFIX}-objcopy
else
EMBTOOLPATH     = D:/EmbedCompiler/riscv64-elf-mingw-20210306
EMBTOOLPREFIX   = ${EMBTOOLPATH}/bin/riscv64-unknown-elf
CC              = ${EMBTOOLPREFIX}-gcc.exe
OBJDUMP         = ${EMBTOOLPREFIX}-objdump.exe
OBJCOPY         = ${EMBTOOLPREFIX}-objcopy.exe
endif

ifeq ($(shell uname), Linux)
VCS             = vcs
SIM             = ./simv
WAV             = dve
else
VCS             = D:/iverilog/bin/iverilog.exe
SIM             = D:/iverilog/bin/vvp.exe
WAV             = D:/iverilog/gtkwave/bin/gtkwave.exe
endif

RM              = rm -f
CP              = cp
MV              = mv

# for vcs tools
ifeq ($(shell uname), Linux)
ALLDEFINE       = +define+DUMP_VPD
ALLDEFINE      += +define+TESTBENCH_VCS
else
ALLDEFINE       = -DDUMP_VCD
ALLDEFINE      += -DTESTBENCH_VCS
endif

TBFILES         = ${PROJPATH}/tb/prim_sim.v \
                  ${PROJPATH}/fpga_project/src/ipdefs/gowin_rpll/gowin_rpll.v \
                  ${PROJPATH}/fpga_project/src/ipdefs/gowin_dpb_8x4k/gowin_dpb_8x4k.v \
                  ${PROJPATH}/fpga_project/src/ipdefs/gowin_dpb_32x8k/gowin_dpb_32x8k.v \
                  ${PROJPATH}/tb/core_data_monitor_tb.v \
                  ${PROJPATH}/tb/core_uart_monitor_tb.v \
                  ${PROJPATH}/tb/core_tb.v

# for c/asm tools
INCLUDES        = 

INCFILES        = -I${PROJPATH}/sim/libs \
                  -I${PROJPATH}/sim/libs/_sdk \
                  -I${PROJPATH}/sim/libs/_sdk/systick \
                  -I${PROJPATH}/sim/libs/_sdk/gpio \
                  -I${PROJPATH}/sim/libs/_sdk/timer \
                  -I${PROJPATH}/sim/libs/_sdk/uart \
                  -I${PROJPATH}/sim/libs/_utilities

CFLAGS          = -march=rv32im -mabi=ilp32 -mcmodel=medlow

LDFLAGS         = -Wl,-Map,${TARGET}.map,-warn-common \
                  -Wl,--gc-sections \
                  -Wl,--no-relax \
                  -nostartfiles

LDLIBS          = -lm -lc -lgcc

ASMFILES        = ${PROJPATH}/sim/libs/_startup/start.S \
                  ${PROJPATH}/sim/libs/_startup/trap.S

CFILES          = ${PROJPATH}/sim/libs/_sdk/systick/*.c \
                  ${PROJPATH}/sim/libs/_sdk/timer/*.c \
                  ${PROJPATH}/sim/libs/_sdk/uart/*.c \
                  ${PROJPATH}/sim/libs/_utilities/*.c
